The present invention is generally related to power-up clear circuitry and more specifically related to CMOS power-up clear circuitry useful for integrated circuit designs.
Power-up clear circuitry as such is known in the art. The function of this circuitry is to generate a signal when the supply voltage reaches the operating level. This signal can be used to simply enable the remainder of the circuitry, or to reset the remaining circuitry to a known state. Such circuitry can be incorporated on an integrated circuit chip in order to ensure proper operation of that chip when power is applied.
Present power-up clear circuitry generally employs a latch and threshold detection circuitry. The state of the latch determines whether the chip is in the power-up state or the normal operating state. The threshold detection circuitry enables the latch when the supply voltage is at the operating level. Typically, an external reset signal is provided to reset the latch and end the power-up sequence. This signal can be generated manually, as for example by means of a switch, or by circuitry external to the power-up clear circuitry.
Power-up clear circuitry as presently known has several important drawbacks. One such drawback is that the threshold detect circuitry draws standby power. This draws power away from the remaining circuitry on an integrated circuit chip, and is especially important in low power, CMOS applications.
Another important drawback is that prior art power-up clear circuitry will not necessarily operate properly after a supply voltage transient. If the supply voltage drops below the threshold voltage of devices is on an integrated circuit chip, the logical state of those devices is not guaranteed when supply voltage again rises above the threshold voltage. Present power-up circuitry has the defect that the latch may power-up in the normal operating state if the supply voltage transient is sufficiently short. Thus, although the state of the remainder of the devices may be random, no power-up clear pulse is generated.
Present circuits require an external signal to activate the power-up sequence. Finally, present power-up clear circuitry that is suitable for integrating on a CMOS integrated circuit chip is unduly complex.
It is therefore an object of the present invention to supply CMOS power-up clear circuitry which is suitable for integration on a chip with other circuitry . It is a further object that such power-up clear circuitry ensures that no power-up clear pulse is generated when the supply voltage drops but remains above the device threshold voltage, and further ensures that a power-up clear pulse is always generated if the supply voltage drops below the threshold voltage. It is another object of the present invention that such power-up clear circuitry draw no standby power once the power-up clear pulse has been generated and the remainder of the chip is in normal operation. It is yet another object of the present invention that such power-up clear circuitry is self-executing, and requires no external signal to activate.
Therefore, in accordance with the present invention. power-up clear circuitry includes a threshold detect circuit and a latch. The latch is a preferential cross-coupled latch, and powers-up in a known state. The threshold detect circuitry detects when the supply has reached the operating voltage, and changes the state of the latch. Delay circuitry coupled to the output of the latch causes the power-up clear signal to change to a normal operation state a predetermined time delay after the latch changes state. The delay circuitry also provides signals to the threshold detection circuitry which causes same to switch itself off during normal operating conditions. Supply voltage transient protect circuitry is coupled to the latch, and ensures that the latch will always power-up in a preferred state. This is accomplished by using a charge pump technique and the supply transient protect circuitry to ensure that the latch is completely clear as soon as the supply voltage drops below the threshold voltage.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereafter appear, and for purposes of illustration, but not of limitation, a preferred embodiment is shown in the accompanying drawings.